多公器-4各INPUT、2各OUTPUT

module top;

wire A,B,C,D,SEL,OUT_1,OUT_2;
system_clock #100 clock1(A);
system_clock #200 clock2(B);
system_clock #100 clock3(C);
system_clock #200 clock4(D);
system_clock #400 clock5(SEL);

mux2 a1(OUT_1, OUT_2, A, B, C, D, SEL);

endmodule

module mux2(OUT_1, OUT_2, A, B, C, D, SEL);

output OUT_1,OUT_2;
input A,B,C,D;
input SEL;

mux hi (OUT_1, A, B, SEL);
mux lo (OUT_2, C, D, SEL);

endmodule

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL) ;

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule


module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

begin

#(PERIOD) clk=~clk;

end

always@(posedge clk)

if($time>1000)$stop;

endmodule