真質表轉卡諾圖(考試版)

module top;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock3(D);
adder1 M1(F, A, B, C,D);
endmodule

module adder1(F, A, B, C, D);
output F;
input A,B,C,D;


not I1(notA,A);
not I2(notB,B);
not I3(notC,C);
not I4(notD,D);

and I5(s1,notA,notC,notD);
and I6(s2,A,notC,D);
and I7(s3,B,C,D);
and I8(s4,notA,notB,notC,D);
and I9(s5,A,notB,C,notD);

or I10(F,s1,s2,s3,s4,s5);


endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

真值表轉卡諾圖

一位元加法器

module top;
system_clock #400 clock1(C);
system_clock #200 clock2(A);
system_clock #100 clock3(B);
adder1 M1(Cout, Sum, A, B, C);
endmodule

module adder1(Cout, Sum, A, B, C);
output Cout,Sum;
input A,B,C;


not I1(notA,A);
not I2(notB,B);
not I3(notC,C);

and I4(s1,A,B);
and I5(s2,B,C);
and I6(s3,A,C);
and I7(s4,notA,B,notC);
and I8(s5,A,notB,notC);
and I9(s6,notA,notB,C);
and I10(s7,A,B,C);

or I11(Cout,s1,s2,s3);
or I12(Sum,s4,s5,s6,s7);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

2位元多工器

module top;
wire  [1:0] A,B, OUT;
wire SEL;
system_clock #100 clock1(A[0]);
system_clock #200 clock2(A[1]);
system_clock #100 clock3(B[1]);
system_clock #200 clock4(B[0]);
system_clock #400 clock5(SEL);
mux2 M1(OUT,A,B,SEL);
endmodule
/*兩位元多工器  */
module mux2(OUT,A,B,SEL);
output [1:0] OUT;
input [1:0] A,B;
input SEL;
mux hi(OUT[1],A[1],B[1],SEL);
mux lo(OUT[0],A[0],B[0],SEL);
endmodule
/*一位元多工器  */
module mux(OUT,A,B,SEL);
output OUT;
input  A,B,SEL;
not I5(sel_n,SEL);
and I6(sel_a,A,SEL);
and I7(sel_b,sel_n,B);
or I4(OUT,sel_a,sel_b);
endmodule
/*系統時脈  */
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
 begin
#(PERIOD/2) clk=~clk;
 end
always@(posedge clk)
 if($time>1000)$stop;
endmodule

多公器-4各INPUT、2各OUTPUT

module top;

wire A,B,C,D,SEL,OUT_1,OUT_2;
system_clock #100 clock1(A);
system_clock #200 clock2(B);
system_clock #100 clock3(C);
system_clock #200 clock4(D);
system_clock #400 clock5(SEL);

mux2 a1(OUT_1, OUT_2, A, B, C, D, SEL);

endmodule

module mux2(OUT_1, OUT_2, A, B, C, D, SEL);

output OUT_1,OUT_2;
input A,B,C,D;
input SEL;

mux hi (OUT_1, A, B, SEL);
mux lo (OUT_2, C, D, SEL);

endmodule

module mux(OUT, A, B, SEL);

output OUT;

input A,B,SEL;

not I5 (sel_n, SEL) ;

and I6 (sel_a, A, SEL);

and I7 (sel_b, sel_n, B);

or I4 (OUT, sel_a, sel_b);

endmodule


module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial clk=0;

always

begin

#(PERIOD) clk=~clk;

end

always@(posedge clk)

if($time>1000)$stop;

endmodule

多工器的波形

第一次製作

新的開始