module top;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock3(D);
adder1 M1(F, A, B, C,D);
endmodule
module adder1(F, A, B, C, D);
output F;
input A,B,C,D;
not I1(notA,A);
not I2(notB,B);
not I3(notC,C);
not I4(notD,D);
and I5(s1,notA,notC,notD);
and I6(s2,A,notC,D);
and I7(s3,B,C,D);
and I8(s4,notA,notB,notC,D);
and I9(s5,A,notB,C,notD);
or I10(F,s1,s2,s3,s4,s5);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
begin
#(PERIOD/2) clk=~clk;
end
always@(posedge clk)
if($time>1000)$stop;
endmodule
